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EM78P5840/41/42
8-BIT MICRO-CONTROLLER
Version 2.6
ELAN MICROELECTRONICS CORP. No. 12, Innovation 1st RD., Science-Based Industrial Park Hsin Chu City, Taiwan, R.O.C. TEL: (03) 5639977 FAX: (03) 5630118
Version History
Specification Revision History
Version eFHP5830B 1.0 eFHP5840 2.0 Content Initial version 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 1. 1. 2. 1. 2. 1. 2. 1. 2. 1. 2. Change counter1 external input pin from PC2 to P94 Modify P60, P61 to INPUT/OUTPUT IO Remove P71 internal pull high function Modify control register initial value Remove 256 byte Data RAM Remove SPI function Add IRC and ERIC oscillator function Decrease Stack from 16 to 8 Add Counter1 external source (from IO pad) Remove Counter2 Add the relative of ERIC oscillating frequency and external R Add IRC mode CLK trimming control in code option. Modify PORT9 sink/driver current. Rename "ERC mode" to "ERIC mode" Modify the relative between ERIC mode's oscillating CLK and the value of external resister. Change pin name from "ERCI" to "ERIC" Change the descript about CONT reg bit7 Remove Crystal mode's Idle application Modify operating temperature Rename eFH78P5840/41/42 / EM78P5840/41/42 Change IRC frequency deviation from +/- 5% to +/- 10%
2.1 2.2 2.3
2.4 2.5 2.6
Relative to EM785840's ROM-less, OTP and mask:
ROM-less ICE5830 OTP EM78P5840 EM78P5841 EM78P 5842 Mask EM785840 EM785841 EM785842
Table1: the relation between EM78P5830 and EM78P5840 series: EM78P5830 series EM78P5840 series PACKAGE EM78P5830CP EM78P5840P 18 pin PDIP EM78P5830ACP EM78P5830CM EM78P5840M 18 pin SOP EM78P5830ACM EM78P5830BP EM78P5841P 20 pin PDIP EM78P5830ABP EM78P5830BM EM78P5841M 20 pin SOP EM78P5830ABM EM78P5830FP EM78P5842P 24 pin PDIP EM78P5830AFP EM78P5830FM EM78P5842M 24 pin SOP EM78P5830AFM
EM78P5840/5841/5842 8-bit Micro-controller
Table2: the major differences between EM78P5830 and EM78P5840 series: EM78P5830 series EM78P5840 series CID RAM 256 byte NA ERIC mode NA Under 6M Hz IRC mode NA 2M / 4M Hz WDT source Crystal or PLL IRC1 External CNT1 input NA Shared with P94 P71 pull high Internal pull high External pull high /RESET pin /RESET only Shared with P71 PLLC pin PLLC only Shared with P70 and ERCI XIN, XOUT Crystal input Shared with P60 and P61 Table3: the major differences between ICE5840, EM78P5840 and EM785840: ICE5840 EM78P5840 series CID RAM 1024 byte NA CID RAM address auto V NA +1 CNT1 (**) 8 bit counter 8 bit counter
EM785840 series NA NA
8 or 16 (shared with CNT2) bit counter CNT2 (**) V X V STACK 12 8 8 ** CNT2 is only exist on EM78P5840/41/42 and EM785840/41/42, CNT2 is un-support on ICE5840. Table4: Differences between EM78P5840, EM78P5841 and EM78P5842: EM78P5840 EM78P5841 Pin count 18 20 PWM X 2 channel IO (MAX) 16 18
EM78P5842 24 2 channel 22
User Application Note
(Before using this chip, take a look at the following description note, it includes important messages.) 1. There are some undefined bits in the registers. The values in these bits are unpredicted. These bits are not allowed to use. We use the symbol "-" in the spec to recognize them. A fixed value must be write in some specific unused bits by software or some unpredicted wrong will occur. 2. You will see some names for the register bits definitions. Some name will be appear very frequently in the whole spec. The following describes the meaning for the register's definitions such as bit type, bit name, bit number and so on.
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* This specification is subject to change without notice.
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RA PAGE0
7 RAB7 R/W -0 Bit type Bit name Bit number Register name and its page
6 RAB6 R/W -0
read/write (default value=0)
5 BAB5 R-1
4 RAB4 R/W -1
read/write (default value=1)
3 -
2 RAB2 R
1 RAB1 R-0
0 RAB0 R/W
read/write (w/o default value)
read only (w/o default value)
(undefined) not allowed to use read only (default value=1) read only (default value=0)
3. Always set IOCC PAGE1 bit 0 = 1 otherwise partial ADC function cannot be used (in ICE5830). 4. Please do not switch MCU operation mode from normal mode to sleep mode directly. Before into sleep mode, please switch MCU to green mode. 5. While switching main clock (regardless of high freq to low freq or on the other hand), adding 6 instructions delay (NOP) is required. 6. Offset voltage will effect ADC's result, please refer to figure 19 to detail. 7. Please do not connect unnecessary circuit on OTP burner pins during burning the OTP ROM.
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* This specification is subject to change without notice.
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I. General Description
The EM78P5840 series are 8-bit RISC type microprocessor with low power, high speed CMOS technology. There are 4Kx13 bits Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides security bits and some One time programmable Option bits to protect the OTP memory code from any external access as well as to meet user's options. This integrated single chip has an on_chip watchdog timer (WDT), program OTP-ROM, RAM, programmable real time clock/counter, internal interrupt, power down mode, dual PWM (Pulse Width Modulation), 8-channel 10-bit A/D converter and tri-state I/O.
II. Feature
CPU * Operating voltage : 2.2V~5.5V at main CLK less then 3.58MHz.
E E E E E E E E E Main CLK(Hz) Under 3.58M 14.3M Operating Voltage(min) 2.2V 3.6V 4k x 13 on chip Electrical One Time Programmable Read Only Memory (OTP-ROM) 144 x 8 on chip general propose RAM Up to 19 bi-directional and 3 input only general purpose I/O 8 level stack for subroutine nesting 8-bit real time clock/counter (TCC) One 8-bit counter interrupt On-chip watchdog timer (WDT) 99.9H single instruction cycle commands Three action modes in Crystal mode (Main clock can be programmed to 3.58M or 14.3M Hz) Mode CPU status Main clock 32.768kHz clock status Sleep mode Turn off Turn off Turn off Green mode Turn on Turn off Turn on Normal mode Turn on Turn on Turn on 2 level Normal mode frequency: 3.58M and 14.3MHz. Input port interrupt function Dual clocks operation (Internal PLL main clock , External 32.768KHz)
E E E
Operating frequency mode
E Crystal mode (XIN,XOUT pin connect external crystal and capacitance) E ERIC mode (ERCI pin connect resister to VDD) E IRC mode
PWM
E Dual PWM (Pulse Width Modulation) with 10-bit resolution E Programmable period (or baud rate) E Programmable duty cycle
ADC * Operating : 2.5Va 5.5V
Converter Rate Operating Voltage(min) 74.6K 3.5V 37.4K 3.0V 18.7K 2.5V 9.3K 2.5V
* 8 channel 10-bit successive approximation A/D converter * Internal (VDD) reference voltage POR * Power-on reset PACKAGE
EM78P5840M EM78P5840P 18 pin SOP, EM78P5841M 18 pin PDIP, EM78P5841P 20 pin SOP, EM78P5842M 20 pin PDIP, EM78P5842P 24 pin SOP 24 pin PDIP
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* This specification is subject to change without notice.
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III. Application
General products application.
IV. Pin Configuration
CIN/P94 P95 P96 AVDD
PLLC/ERIC
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
AD8/P93 AD7/P92 AD2/P91 AD1/P90 INT3/P73 /RESET/P71/INT1 XOUT/P60 XIN/P61 AD3/P62
/P70/INT0 AVSS AD6/P65 AD5/P64 AD4/P63
(a)
CIN/P94
CIN/P94 P95 P96 AVDD PLLC/ERIC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AD8/P93 AD7/P92 AD2/P91 AD1/P90 PWM2/PC2 PWM1/PC1 INT3/P73
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
AD8/P93 AD7/P92 AD2/P91 AD1/P90 PWM2/PC2 PWM1/PC1 INT3/P73 P74 P75 P76 /RESET/P71/INT1 XOUT/P60
P95 P96 P97 AVDD
PLLC/ERIC
/P70/INT0
AVSS AD6/P65 AD5/P64 AD4/P63 AD3/P62
/P70/INT0 AVSS AD6/P65 AD5/P64 AD4/P63 AD3/P62 XIN/P61
/RESET/P71/INT1 XOUT/P60 XIN/P61
(b)
(c)
Fig.1: EM78P5840 series pin assignment. (a): EM78P5840M, EM78P5840P (b): EM78P5841M, EM78P5841P (c): EM78P5842M, EM78P5842P
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* This specification is subject to change without notice.
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V. Functional Block Diagram
CPU DATA RAM CONTROL REGISTER
TIMING CONTROL
TIMER TCC COUNTER1 COUNTER2 WDT
I/O PORT
ROM
PWM 10-bit A/D
Fig.2a Block diagram
XIN XOUT PLLC
WDT timer ROM R2 STACK
Oscillator timing control R1(TCC)
Prescaler Interrupt control General RAM Instruction decoder R4 Instruction register R3 R5 ALU
Control sleep and wakeup on I/O port
ACC
DATA & Control Bus
IOC6 R6 PWM 10-bit A/D PORT6
IOC7 R7 PORT7
IOC9 R9 PORT9
IOCC RC PORTC
P60~P61
P62~P66
P71
P70 P73~P76
P90~P97
PC1~PC2
Fig.2b Block diagram
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* This specification is subject to change without notice.
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VI. Pin Descriptions
PIN POWER AVDD AVSS CLOCK XIN XOUT PLLC OSC CIN I/O POWER POWER I O I I I DESCRIPTION Power Ground Input pin for 32.768 kHz oscillator Output pin for 32.768 kHz oscillator Phase loop lock capacitor, connect a capacitor 0.047u to 0.1u to the ground. ERIC mode clock signal input. This pin is shared with PLLC. Counter1 external CLK input. This pin is shared with P94. Note the frequency of the input CLK must less than 1M Hz. ADC input channel 1. Shared with PORT90 ADC input channel 2. Shared with PORT91 ADC input channel 3. Shared with PORT62 ADC input channel 4. Shared with PORT63 ADC input channel 5. Shared with PORT64 ADC input channel 6. Shared with PORT65 ADC input channel 7. Shared with PORT92 ADC input channel 8. Shared with PORT93 Pulse width modulation output This pin shared with PORTC1 Pulse width modulation output This pin shared with PORTC2 PORT60,1 can be INPUT or OUTPUT port each bit.. These two pins can be used on ERIC and IRC modes. PORT6 can be INPUT or OUTPUT port each bit. PORT70 can be INPUT or OUTPUT port each bit. PORT71 is INPUT only. PORT7 can be INPUT or OUTPUT port each bit. PORT9 can be INPUT or OUTPUT port each bit. PORTC can be INPUT or OUTPUT port each bit. Interrupt sources. Once PORT70 has a falling edge or rising edge signal (controlled by CONT register), it will generate a interruption. Interrupt sources which has the same interrupt flag. Any pin from PORT71 has a falling edge signal, it will generate a interruption. Interrupt sources which has the same interrupt flag. Any pin from PORT73 has a falling edge signal, it will generate a interruption. Low reset
10-bit 8 channel A/D AD1 I (P90) AD2 I (P91) AD3 I (P62) AD4 I (P63) AD5 I (P64) AD6 I (P65) AD7 I (P92) AD8 I (P93) PWM PWM1 O PWM2 IO P60 ~ P61 P62 ~P65 P70 P71 P73~P76 P90 ~ P97 PC1 ~ PC2 INT0 INT1 INT3 /RESET O
I/O I/O I/O I I/O I/O I/O (PORT70) (PORT71) PORT73 I
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* This specification is subject to change without notice.
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VII. Functional Descriptions VII.1 Operational Registers
Register configuration
Addr 00 01 02 03 04 05 06 07 R PAGE registers R PAGE0 R PAGE1 R PAGE2 Indirect addressing TCC PC Page, Status RAM bank, RSR Program ROM page Port6 I/O data Port7 I/O data ADC MSB output data R PAGE3
08 09 Port9 I/O data 0A PLL, Main clock, WDTE 0B 0C 0D 0E 0F 10 : 1F 20 : 3F PortC I/O data Interrupt flag Interrupt flag 16 bytes Common registers
ADC output data buffer Counter1 data
PWM control Duty of PWM1 PWM1 control Duty of PWM1 Period of PWM1 Duty of PWM2 PWM2 control Duty of PWM2 Period of PWM2
Bank0 Common registers (32x8 for each bank)
Bank1
Bank2
Bank3
*Address 00~0F with page0~page3 are special registers. Address 10~1F are global with general purpose memory. By setting MOV instruction, MCU can read or write these register directly and RAM bank select bits (RB1, RB0 in R4 page0) will be ignored. Address 20~ 3F are general purpose RAM too, but user must indicate the bank number before access data.
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* This specification is subject to change without notice.
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IOC PAGE registers IOC PAGE0 IOC PAGE1
Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D
Port6 I/O control Port7 I/O control Port9 I/O control
Port6 switches Port7 pull high
ADC control Clock source (CN1) Prescaler(CN1)
0E Interrupt mask 0F Interrupt mask 10 : 1F 20 : 3F * IOC register are special registers. User can use instruction "IOW" to write data or "IOR" to read data.
VII.2 Operational Register Detail Description
R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). Example: Mov A, @0x20 ;store a address at R4 for indirect addressing Mov 0x04, A Mov A, @0xAA ;write data 0xAA to R20 at bank0 through R0 Mov 0x00, A
R1 (TCC)
TCC data buffer. Increased by 16.384KHz or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register.
R2 (Program Counter)
The structure is depicted in Fig.3. Generates 4k x 13 external ROM addresses to the relative programming instruction codes. "JMP" instruction allows the direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''.
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"ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. "TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change. The most significant bit (A10~A11) will be loaded with the contents of bit PS0~PS1 in the status register (R5 PAGE0) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction. If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will store ACC, R3 status and R5 PAGE automatically, and they will be restored after instruction RETI.
R5(PAGE)
CALL and INTERRUPT A9 A8 A7~A0 RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 store ACC,R3,R5(PAGE) restore
A11 A10 00 01 10 11
PAGE0 00000~003FF PAGE1 00400~007FF PAGE2 00800~00BFF PAGE3 00C00~00FFF
Fig.3 Program counter organization R3 (Status, Page selection)
(Status flag, Page selection bits) 7 6 5 4 3 2 1 0 RPAGE1 RPAGE0 IOCPAGE T P Z DC C R/W-0 R/W-0 R/W-0 R R R/W R/W R/W Bit 0(C) : Carry flag Bit 1(DC) : Auxiliary carry flag Bit 2(Z) : Zero flag Bit 3(P) : Power down bit Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4(T) : Time-out bit Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
EVENT WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep Power up Low pulse on /RESET T 0 0 1 1 x P 0 1 0 1 X x : don't care REMARK
Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page Please refer to Fig.4 control register configuration for details. 0/1 IOC page0 / IOC page1 Bit 6(RPAGE0 ~ RPAGE1) : change R5 ~ RE to another page Please refer to VII.1 Operational registers for detail register configuration.
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* This specification is subject to change without notice.
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(RPAGE1,RPAGE0) (0,0) (0,1) (1,0) (1,1) R page # selected R page 0 R page 1 R page 2 R page 3
R4 (RAM selection for common registers R20 ~ R3F)
(RAM selection register) 7 6 5 4 3 2 1 0 RB1 RB0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 R/W-0 R/W-0 R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to R3F).. Please refer to VII.1 Operational registers for details.
R5 (Program page selection, PWM control)
PAGE0 (PORT5 I/O data register, Program page register) 7 6 5 4 3 2 X X X X 0 0 R/W-0 R/W-0 Bit 0 ~ Bit 1 (PS0 ~ PS1) : Program page selection bits PS1 PS0 Program memory page (Address) 0 0 Page 0 0 1 Page 1 1 0 Page 2 1 1 Page 3 1 PS1 R/W-0 0 PS0 R/W-0
User can use PAGE instruction to change page to maintain program page by user. Bit2~Bit3 : (undefined) These 2 bits must clear to 0 or MCU will access wronging program code. Bit4~Bit7: (undefined) not allowed to use PAGE1, PAGE2 (Unused registers)
These two registers are not allowed to used.
PAGE3 (PWMCON) 7 6 5 4 3 2 1 PWM2E PWM1E T2EN T1EN T2P1 T2P0 T1P1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 1 ( T1P0 ~ T1P1 ): TMR1 clock prescale option bits. T1P1 T1P0 Prescale 0 0 1:2(Default) 0 1 1:8 1 0 1:32 1 1 1:64 Bit 2 ~ Bit 3 ( T2P0 ~ T2P1 ): TMR2 clock prescale option bits. T2P1 T2P0 Prescale 0 0 1:2(Default) 0 1 1:8
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0 T1P0 R/W-0
* This specification is subject to change without notice.
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1 0 1:32 1 1 1:64 Bit 4 (T1EN): TMR1 enable bit 0 TMR1 is off (default value). 1 TMR1 is on. Bit 5 (T2EN): TMR2 enable bit 0 TMR2 is off (default value). 1 TMR2 is on. Bit 6 (PWM1E): PWM1 enable bit 0 PWM1 is off (default value), and its related pin carries out the PC1 function; 1 PWM1 is on, and its related pin will be set to output automatically. Bit 7 (PWM2E): PWM2 enable bit 0 PWM2 is off (default value), and its related pin carries out the PC2 function. 1 PWM2 is on, and its related pin will be set to output automatically.
R6 (PORT6 I/O data, PWM control)
PAGE0 (PORT6 I/O data register) 7 6 5 4 3 2 1 0 X X P65 P64 P63 P62 P61 P60 R/W R/W R/W R/W R/W R/W Bit0 ~ Bit1 (P60 ~ P61): PORT60 and PORT61 can be used on IRC and ERIC mode. In these two mode, PORT60 and PORT61 will defined to general purpose IO. In crystal mode, PORT60 and PORT61 are defined to crystal input (XIN and XOUT) pins and these two bits are undefined. Bit2 ~ Bit6 (P62 ~ P65): 4-bit PORT6(2~5) I/O data register User can use IOC register to define input or output each bit. Bit6 ~ Bit7 : Unused register. These bits are not allowed to use. PAGE1, PAGE2 : (undefined) not allowed to use
These two registers are not allowed to use.
PAGE3 (DT1L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle of PWM1) 7 6 5 4 3 2 1 0 PWM1[7] PWM1[6] PWM1[5] PWM1[4] PWM1[3] PWM1[2] PWM1[1] PWM1[0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 A specified value keeps the output of PWM1 to stay at high until the value matches with TMR1.
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* This specification is subject to change without notice.
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PAGE0 (PORT7 I/O data register) 7 6 5 4 3 2 1 0 X P76 P75 P74 P73 X P71 P70 R/W R/W R/W R/W R R/W Bit0 (P70): PORT70 is a multi-function pin. In Crystal mode, by setting P70S in code option, PORT70 will be general purpose IO or PLLC. Please do not enable PLL function if PORT70 defined to IO. In IRC or ERIC mode, this pin will defined to PORT70 and P70S will be ignored. P70 is PORT70 I/O data register and user can use IOC register to define input or output each bit. Bit1 (P71): PORT71 is shared with /RESET pin. By setting P71S in code option, PORT71 will defined to INPUT pin or /RESET pin. This register is a read only bit. P71 dose not support internal pull high function. If user want to use P71 interrupt, external pull high is necessary. Bit3 ~ Bit6 (P73 ~ P76): 4 - bit PORT7 I/O data register User can use IOC register to define input or output each bit.
PAGE1 (ADC resolution selection bit and ADC MSB output data)
7 6 5 4 3 2 1 0 X X AD9 AD8 X ADRES 0 0 R R R/W-0 R-0 R-0 Bit 0~Bit 1: Undefined register. These two bits are not allowed to use. These bits must clear to 0. Bit 2(ADRES) : Resolution selection for ADC 0 ADC is 8-bit resolution When 8-bit resolution is selected, the most significant(MSB) 8-bit data output of the internal 10-bit ADC will be mapping to RB PAGE1 so R7 PAGE1 bit 4 ~5 will be of no use. 1 ADC is 10-bit resolution When 10-bit resolution is selected, 10-bit data output of the internal 10-bit ADC will be exactly mapping to RB PAGE1 and R7 PAGE1 bit 4 ~5. Bit 3 : (undefined) not allowed to use Bit 4 ~ Bit 5(AD8 ~ AD9) : The most significant 2 bit of 10-bit ADC conversion output data Combine there two bits and RB PAGE1 as complete 10-bit ADC conversion output data. Bit 6 ~ Bit 7 : (undefined) not allowed to use PAGE2 : (undefined) not allowed to use PAGE3 (DT1H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PWM1[9] PWM1[8] R-0 R-0 R-0 R-0 R-0 R-0 R/W-0 R/W-0 Bit 0 ~ Bit 1 (PWM1[8] ~ PWM1[9]): The Most Significant two bits of PWM1 Duty Cycle Bit 2 ~ Bit 7 : Unused.
R8 (Data RAM address, PWM1 period)
PAGE0: (undefined) not allowed to use PAGE1: (undefined) not allowed to use PAGE2: (undefined) not allowed to use PAGE3 (PRD1: Period of PWM) 7 6 5 4 3 2 1 0 PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 The content of this register is a period (time base) of PWM1. The frequency of PWM1 is the reverse of the period.
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* This specification is subject to change without notice.
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PAGE0 (PORT9 I/O data register) 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register User can use IOC register to define input or output each bit. PAGE1: (undefined) not allowed to use PAGE2: (undefined) not allowed to us PAGE3 (DT2L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle of PWM2) 7 6 5 4 3 2 1 0 PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 A specified value keeps the output of PWM2 to stay at high until the value matches with TMR2.
RA (PLL, Main clock selection, Watchdog timer)
PAGE0 (PLL enable bit, Main clock selection bits, Watchdog timer enable bit) 7 6 5 4 3 2 1 0 PLLEN CLK2 CLK1 CLK0 X X WDTEN 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0(WDTEN) : Watch dog control bit. 0/1 disable/enable User can use WDTC instruction to clear watch dog counter. The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during the green mode or normal mode by software programming. Without presacler, the WDT time-out period is approximately 18 ms. Bit 1~Bit 2 : Unused Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits on Crystal mode. These three bits are unused on IRC and ERIC mode.
In Crystal mode:
User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below. PLLEN CLK2 CLK1 CLK0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 don't care don't care don't care Sub clock 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz MAIN clock 3.582MHz 3.582MHz 3.582MHz 3.582MHz 14.3MHz 14.3MHz 14.3MHz 14.3MHz don't care CPU clock 3.582MHz (Normal mode) 3.582MHz (Normal mode) 3.582MHz (Normal mode) 3.582MHz (Normal mode) 14.3MHz (Normal mode) 14.3MHz (Normal mode) 14.3MHz (Normal mode) 14.3MHz (Normal mode) 32.768kHz (Green mode)
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register. This bit is only used in crystal mode. In RC mode, this bit will be ignored. 0/1 disable PLL/enable PLL
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If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode (low frequency, 32768 Hz).
3.58MHz, 14.3MHz
CLK2 ~ CLK0
PLL circuit
ENPLL
1 switch 0
System clock
Sub-clock 32.768kHz
Fig.4 The relation between 32.768kHz and PLL
Bit 7: Unused register. Always keep this bit to 0 or some un-expect error will happen! Next table show the status after wake-up and the wake-up sources list Wakeup signal SLEEP mode RA(7,6)=(0,0) + SLEP No function
TCC time out IOCF bit0=1 COUNTER1 time out IOCF bit1=1 WDT time out PORT7 (0,1,3)
No function Reset and jump to address 0 Reset and Jump to address 0
PORT70 's wakeup function is controlled by IOCF bit 3. It's falling edge or rising edge trigger (controlled by CONT register bit7). PORT71 's wakeup function is controlled by IOCF bit 4. It's falling edge trigger. PORT73 's wakeup function is controlled by IOCF bit 5. It is falling edge trigger. PAGE1,2 : (undefined) not allowed to use PAGE3 (DT2H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM2) 7 6 5 4 3 2 1 0 X X X X X X PWM2[9] PWM2[8] R/W-0 R/W-0 Bit 0 ~ Bit 1 (PWM2[8] ~ PWM2[9]): The Most Significant Byte of PWM1 Duty Cycle A specified value keeps the PWM1 output to stay at high until the value matches with TMR1. Bit 2 ~ Bit 7 : (undefined) not allowed to use
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* This specification is subject to change without notice.
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EM78P5840/5841/5842 8-bit Micro-controller RB (ADC input data buffer)
PAGE0 : (undefined) not allowed to use PAGE1 (ADC output data register) 7 6 5 4 3 2 1 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R R R R R R R R Bit 0 ~ Bit 7 (AD0 ~ AD7) : The last significant 8 bit of 10-bit or whole of 8 bit resolution ADC conversion output data. Combine there 8 bits and R7 PAGE1 bit4~5 as complete 10-bit ADC conversion output data in 10 bit resolution mode. PAGE 2 (undefined) not allowed to use PAGE3 (PRD2: Period of PWM2) 7 6 5 4 3 2 1 0 PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 The content of this register is a period (time base) of PWM2. The frequency of PWM2 is the reverse of the period.
RC (PORTC I/O data, Counter1 data)
PAGE0 (PORT9 I/O data register) 7 6 5 4 3 2 1 0 X X X X X PC2 PC1 X R/W R/W Bit 1 ~ Bit 2 (PC1 ~ PC2) : PORTC1,PORTC2 I/O data register User can use IOC register to define input or output each bit. Bit 0; Bit 3~Bit 7: (undefined) not allowed to use.(These bits are not sure to 0 or 1 ) PAGE1 (Counter1 data register) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CN17 CN16 CN15 CN14 CN13 CN12 CN11 CN10 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7 (CN10 ~ CN17) : Counter1's buffer that user can read and write. Counter1 is a 8-bit up-counter with 8-bit prescaler that user can use RC PAGE1 to preset and read the counter.(write preset) After a interruption , it will reload the preset value. Example for writing : MOV 0x0C, A ; write the data at accumulator to counter1 (preset) Example for reading : MOV A, 0x0C ; read the data at counter1 to accumulator PAGE2,3 (undefined) not allowed to use.
RD (Undefined register)
PAGE0 (Unused) 7 6 5 4 3 2 1 0 X 0 X 0 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W R/W R/W Bit 0 ~Bit 2 : These three bits must clear to 0 or MCU power consumption will increase. Bit 3 , Bit 7 : (undefined) not allowed to use Bit4 ~ Bit6 : These 3 bits are unused in mask/OTP EM785840, but they are used for ICE5830. About the definition of these 3 bits, please refer to appendix II. In ICE5830, please clear bit4, bit5 and bit6 to 0. PAGE1,2,3 (undefined) not allowed to use.
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* This specification is subject to change without notice.
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EM78P5840/5841/5842 8-bit Micro-controller RE (Interrupt flag)
PAGE0 (Interrupt flag) 7 6 5 4 3 2 1 0 PWM2 0 ADI PWM1 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit0 ~ Bit3, Bit6: These four bits must clear to 0 or unable to expect error will occur . Bit 4(PWM1) : PWM1 one period reach interrupt flag. Bit 5 (ADI) : ADC interrupt flag after a sampling Bit 7 (PWM2) : PWM2 (Pulse Width Modulation channel 2) interrupt flag Set when a selected period is reached, reset by software. PAGE2,3 (undefined) not allowed to use.
RF (Interrupt status)
(Interrupt status register) 7 6 5 4 3 2 1 0 INT3 0 0 INT1 INT0 0 CNT1 TCIF R/W-0 R/W-X R/W-X R/W-0 R/W-0 R/W-X R/W-0 R/W-0 "1" means interrupt request, "0" means non-interrupt Bit 0(TCIF) : TCC timer overflow interrupt flag Set when TCC timer overflows. Bit 1(CNT1) : counter1 timer overflow interrupt flag Set when counter1 timer overflows. Bit 2,5,6: Unused (These bits are not sure to 0 or 1. When programmer determine what interrupt occur in subroutine, be care to note these bits) Bit 3(INT0): By setting PORT70 to general IO, INT0 will define to PORT70 pin's interrupt flag. If PORT70 has a falling edge/rising edge (controlled by CONT register) trigger signal, CPU will set this bit. If setting the pin to PLLC or OSCI, PORT70 interrupt will un-exist and INT0 register will be ignored. Bit 4(INT1): By setting PORT71 to general IO, INT1 will define to PORT71 pin's interrupt flag. External pull high circuit is needed for PORT71 interrupt operation. If PORT71 has a falling edge trigger signal, CPU will set this bit. If setting the pin to /RESET, PORT71 interrupt will un-exist and INT1 register will be ignored. Bit 7(INT3): External PORT73 pin interrupt flag. If PORT73 has a falling edge trigger signal, CPU will set this bit. IOCF is the interrupt mask register. User can read and clear. Trigger edge as the table Signal TCC COUNTER1 INT0 INT1 INT3 Trigger Time out Time out Falling Rising edge Falling edge Falling edge
R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : all are general purpose registers.
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* This specification is subject to change without notice.
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VII.3 Special Purpose Registers
A (Accumulator)
Internal data transfer, or instruction operand holding It's not an addressable register.
CONT (Control Register)
7 6 5 4 3 2 P70EG INT TS RETBK PAB PSR2 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1 PSR1 R/W-1 0 PSR0 R/W-1
Bit 3(PAB) : Prescaler assignment bit 0/1 TCC/WDT Bit 4(RETBK) : Return value backup control for interrupt routine 0/1 disable/enable When this bit is set to 1, the CPU will store ACC,R3 status and R5 PAGE automatically after an interrupt is triggered. And it will be restored after instruction RETI. When this bit is set to 0, the user need to store ACC, R3 and R5 PAGE in user program. Bit 5(TS) : TCC signal source 0 Internal instruction cycle clock 1 IRC output Bit 6 (INT) : INT enable flag 0 interrupt masked by DISI or hardware interrupt 1 interrupt enabled by ENI/RETI instructions Bit 7 (P70EG): If switch port70 to INT0 input, P70EG can select the interrupt toggle type. 0 P70 's interruption source is a rising edge signal and falling edge signal. 1 P70 's interruption source is a falling edge signal. CONT register is readable (CONTR) and writable (CONTW). TCC and WDT : There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT only at the same time. An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register. See the prescaler ratio in CONT register. Fig.5 depicts the circuit diagram of TCC/WDT.
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* This specification is subject to change without notice.
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OSCM1,0
PLL Output IRC2 oscillator ERC oscillator
IRC1 (32K)
Fig.5 Block diagram of TCC WDT
IOC5 (Unused)
PAGE0 (Unused) 7 6 5 4 3 2 1 0 0 0 0 R/W R/W R/W Bit0~4 : (undefined) not allowed to use Bit5~Bit7(Unused) : These three bits must clear to 0 or MCU power consumption will increase. The default value in these 3 bits are "1". Please clear them to "0" when init MCU. PAGE1 (undefined) not allowed to use.(This page is not sure to 0 or 1 )
IOC6 (PORT6 I/O control, P6* pins switch control)
PAGE0 (PORT6 I/O control register) 7 6 5 4 3 2 1 0 0 0 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit0~Bit1: In crystal mode, these two bits are unused registers. In IRC or ERIC mode, PORT60 and PORT61 are I/O direction control register. Bit 2 ~ Bit 5 (IOC62 ~ IOC65) : PORT6(2~5) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance Bit6~Bit7 (Unused): These2 bits must clear to 0 or MCU power consumption will increase. The default value in these 2 bits are "1". Please clear them to "0" when init MCU.
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* This specification is subject to change without notice.
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PAGE1 (P6* pins switch control register)
7 6 5 4 3 2 1 X 0 P65S P64S P63S P62S P91S R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADC channel 1 and channel 2 are shared with PORT90 and PORT91. Bit 0(P90S) : Select normal I/O PORT90 pin or channel 1 input AD1 pin of ADC 0 P90 (I/O PORT90) pin is selected 1 AD1 (Channel 1 input of ADC) pin is selected Bit 1(P91S) : Select normal I/O PORT91 pin or channel 2 input AD2 pin of ADC 0 P91 (I/O PORT91) pin is selected 1 AD2 (Channel 2 input of ADC) pin is selected Bit 2(P62S) : Select normal I/O PORT62 pin or channel 3 input AD3 pin of ADC 0 P62 (I/O PORT62) pin is selected 1 AD3 (Channel 3 input of ADC) pin is selected Bit 3(P63S) : Select normal I/O PORT63 pin or channel 4 input AD4 pin of ADC 0 P63 (I/O PORT63) pin is selected 1 AD4 (Channel 4 input of ADC) pin is selected Bit 4(P64S) : Select normal I/O PORT64 pin or channel 5 input AD5 pin of ADC 0 P64 (I/O PORT64) pin is selected 1 AD5 (Channel 5 input of ADC) pin is selected Bit 5(P65S) : Select normal I/O PORT65 pin or channel 6 input AD6 pin of ADC 0 P65 (I/O PORT65) pin is selected 1 AD5 (Channel 6 input of ADC) pin is selected Bit 6: Unused register. Please clear this bit to 0 or ADC result will wronging. Bit 7: Unused register. This bit is nor allowed to use. 0 P90S R/W-0
IOC7 (PORT7 I/O control, PORT7 pull high control)
PAGE0 (PORT7 I/O control register) 7 6 5 4 3 2 1 0 X IOC76 IOC75 IOC74 IOC73 X X IOC70 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit0(IOC70): PORT70 pin will defined to general purpose IO, PLLC or OSC by setting code option. In IRC mode or crystal mode(only at code option P70S =0 ), PORT70 pin will be a general purpose IO. IOC70 is PORT70 pin's I/O direction control register. 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance Bit1 (Unused) : This bit is unused registers. By setting P71S = 1 in code option, PORT71 pin will be a INPUT only pin. Bit2; Bit7 (Unused) : These 2 bits must clear to 0 or MCU power consumption will increase. The default value in these 3 bits are "1". Please clear them to "0" when init MCU. Bit3~Bit6 (IOC73~IOC76) : PORT7 I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance PAGE1 (PORT7 pull high control register) 7 6 5 4 3 2 1 0 X PH76 PH75 PH74 PH73 X X PH70 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit0: PORT70 pull high control register. This bit only exist on setting PORT70 general purpose IO. 0 disable pull high function. 1 enable pull high function Bit1, Bit7 (Unused): These2 bits must clear to 0 or MCU power consumption will increase. Bit3~Bit6 : PORT7 pull high control register
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* This specification is subject to change without notice.
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0 1 disable pull high function. enable pull high function
IOC8 (Unused), not allowed to use IOC9 (PORT9 I/O control, PORT9 switches)
PAGE0 (PORT9 I/O control register) 7 6 5 4 3 2 1 0 IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 IOC91 IOC90 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : PORT9(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance PAGE1 (Unused) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 **These 8 bits must clear to 0 or Port9 input or output function will wronging
IOCA (Unused)
PAGE0(undefined) not allowed to use PAGE1 Unused 7 6 5 4 3 2 1 0 X X X X AD8S AD7S 0 0 R/W R/W R/W-0 R/W-0 Bit 0(AD7S) : Select normal I/O PORT92 pin or channel 7 input AD7 pin of ADC 0 P92 (I/O PORT92) pin is selected 1 AD7 (Channel 7 input of ADC) pin is selected Bit 1(AD8S) : Select normal I/O PORT93 pin or channel 8 input AD8 pin of ADC 0 P93 (I/O PORT93) pin is selected 1 AD8 (Channel 8 input of ADC) pin is selected Bit3 , Bit6 (Unused) : These 2 bits must clear to 0 or MCU power consumption will increase. Bit2 ~ Bit7 are undefined register, they are not allowed to use.
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* This specification is subject to change without notice.
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EM78P5840/5841/5842 8-bit Micro-controller IOCB (ADC control)
PAGE0 (Unused) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ** This page must clear to 0 or MCU power consumption will increase. The default value in these 8 bits are "1". Please clear them to "0" when init MCU. PAGE1 (ADC control bits) 7 6 5 4 3 2 1 0 IN2 IN1 IN0 ADCLK1 ADCLK0 ADPWR 0 ADST R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0(ADST) : AD converter start to sample By setting to "1", the AD will start to sample data. This bit will be cleared by hardware automatically after a sampling. Bit 1 : (undefined) not allowed to use. This bit must clear to 0. Bit 2(ADPWR) : AD converter power control, 1/0 enable/disable. Bit 3 ~ Bit 4 (ADCLK0 ~ ADCLK1) : AD circuit `s sampling clock source. For Crystal mode: ADCLK1 ADCLK0 0 0 1 1 0 1 0 1 Sampling rate 74.6K 37.4K 18.7K 9.3K Operation voltage >=3.5V >=3.0V >=2.5V >=2.5V
For IRC or ERIC mode, AD converter rate will change by oscillator. The formula for input frequency and AD converter rate is: AD converter rate = oscillator / 4 / (2^ADCLK)/12 For example, if input CLK = 4M Hz: ADCLK1 ADCLK0 0 0 1 0 1 0 Sampling rate 83.3K 41.7K 20.8K Operation voltage >=3.5V >=3.0V >=2.5V
1 1 10.4K >=2.5V * Please avoid AD converter rate over 50K Hz, it maybe decrease ADC's resolution. This is a CMOS multi-channel 10-bit successive approximation A/D converter. Features 74.6kHz maximum conversion speed (Crystal mode) at 5V. Adjusted full scale input Internal (VDD) reference voltage 8 analog inputs multiplexed into one A/D converter Power down mode for power saving A/D conversion complete interrupt Interrupt register, A/D control and status register, and A/D data register
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* This specification is subject to change without notice.
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PLL
fpll
Programmable divider 1/Mx
fs
Divider Nx
fadc
10-bit ADC
ADC output
ADCLK1~ADCLK0
ENPLL
CLK2 ~ CLK0
Fig.6 ADC voltage control logic Bit 5 ~ Bit 7(IN0~ IN2) : Input channel selection of AD converter These two bits can choose one of three AD input. IN2 IN1 IN0 Input Pin 0 0 0 AD1 P90 0 0 1 AD2 P91 0 1 0 AD3 P62 0 1 1 AD4 P63 1 0 0 AD5 P64 1 0 1 AD6 P65 1 1 0 AD7 P92 1 1 1 AD8 P93 *Before switch to the AD channel, please set the corresponding pin as AD input.
IOCC (PORTC I/O control, ADC control)
PAGE0 (PORTC I/O control) 7 6 5 4 3 2 1 0 IOCC2 IOCC1 0 0 0 0 0 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 1 ~ Bit 2 (IOCC1 ~ IOCC2) : PORTC(1~2) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance ** Bit0 , Bit3 ~ Bit7 must clear to 0 or MCU power consumption will increase. The default value in these 6 un-define bits are "1". Please clear them to "0" when init MCU. PAGE1 (PORT switch) 7 6 5 4 3 2 1 0 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W/0 Bit 0: Always set this bit to "1" otherwise partial ADC function cannot be used) Bit 1 ~ Bit 7: (undefined) not allowed to use
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* This specification is subject to change without notice.
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EM78P5840/5841/5842 8-bit Micro-controller IOCD (TONE1 control, Clock source, Prescaler of CN1)
PAGE0 (Reserved) PAGE1 (Clock source and prescaler for COUNTER1) 7 6 5 4 3 2 1 0 X X X CNT1S C1_PSC2 C1_PSC1 C1_PSC0 CNTI/ES R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 2 (C1_PSC0 ~ C1_PSC2) : COUNTER1 prescaler ratio C1_PSC2 C1_PSC1 C1_PSC0 COUNTER1 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 3(CNT1S) : COUNTER1 clock source. This bit will un-effect on RC mode (RC mode's CLK is always equal to oscillator frequency). 0/1 16.384kHz / system clock.
TRL P94 reload
IRC2 ERC Fosc CNTI/ES Fpll OSCM1,0 CNT1S
Prescaler
8-bit Counter Overflow
Timer Interrupt Timer wake up
PSR2..PSR0
Timer EN
Fig 7: Timer CLK source diagram Bit4 ~ Bit6: Unused register. These three bits are not allowed to use. Bit7 (CNTI/ES):Counter source select. CNTI/ES = 0 Timer counter CLK come from system CLK or Crystal output and P94 is defined to general propose IO. CHTI/ES = 1 P94 is defined to input and Timer counter's CLK will come from P94's falling edge.
IOCE (Interrupt mask,)
PAGE0 (Interrupt mask) 7 6 5 4 3 2 1 0 PWM2 0 ADI PWM1 X X X X R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 3 : unused Bit 4(PWM1) : PWM1 one period reach interrupt mask. Bit 5 (ADI) : ADC conversion complete interrupt mask 0/1 disable/enable interrupt There are four registers for A/D converter. Use one bit of interrupt control register (IOCE PAGE0 Bit5) for
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A/D conversion complete interrupt. The status and control register of A/D (IOCB PAGE1 and RE PAGE0 Bit5) responses the A/D conversion status or takes control on A/D. The A/D data register (RB PAGE1) stores A/D conversion result. ADI bit in IOCE PAGE0 register is end of A/D conversion complete interrupt enable/disable. It enables/disables ADI flag in RE register when A/D conversion is complete. ADI flag indicates the end of an A/D conversion. The A/D converter sets the interrupt flag, ADI in RE PAGE0 register when a conversion is complete. The interrupt can be disabled by setting ADI bit in IOCE PAGE0 Bit5 to `0'. The A/D converter has eight analog input channels AD1~AD8 multiplexed into one sample and hold to A/D module. Reference voltage can be driven from internal power. The A/D converter itself is of an 10-bit successive approximation type and produces lost significant 8-bit result in the RB PAGE1 and most significant 2 bit to R7 PAGE1 bit4, bit5. A conversion is initiated by setting a control bit ADST in IOCB PAGE1 Bit0. Prior to conversion, the appropriate channel must be selected by setting IN0~IN2 bits in RE register and allowed for enough time to sample data. Every conversion data of A/D need 12-clock cycle time. The minimum conversion time required is 13 us (73K sample rate). ADST Bit in IOCB PAGE1 Bit0 must be set to begin a conversion. It will be automatically reset in hardware when conversion is complete. At the end of conversion, the START bit is cleared and the A/D interrupt is activated if ADI in IOCE PAGE0 Bit5 = 1. ADI will be set when conversion is complete. It can be reset in software. If ADI = 0 in IOCE PAGE0 Bit5, when A/D start conversion by setting ADST(IOCB PAGE1 Bit0) = 1 then A/D will continue conversion without stop and hardware won't reset ADST bit. In this condition, ADI is deactived. After ADI in IOCE PAGE0 bit5 is set, ADI in RE PAGE0 bit5 will activate again. To minimum operating current , all biasing circuits in the A/D module that consume DC current are power down when ADPWR bit in IOCB PAGE1 Bit2 register is a '0'. When ADPWR bit is a `1', A/D converter module is operating.
1
2
3
4
5
6
7
8
9
10
START SAMPLE ADI(IOCE PAGE0 bit5 ) =1 ADI(RE PAGE0 bit 5) DATA Clear by software
Fig.8 A/D converter timing
Bit 6: Undefined register. Please clear this bit to 0. Bit 7 (PWM2) : PWM2 interrupt enable bit 0/1 disable/enable interrupt
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* This specification is subject to change without notice.
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(Interrupt mask register) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INT3 X X INT1 INT0 X CNT1 TCIF R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~1; 3~4 ; Bit 7 : interrupt enable bit 0 disable interrupt 1 enable interrupt Bit 2, 5~6 : (remain these values to "0"othwise it will generate unpredicted interrupts)
The status after interrupt and the interrupt sources list as the table below.
Interrupt signal TCC time out IOCF bit0=1 And "ENI" ENI DISI SLEEP mode RESET and Jump to address 0 No function No function GREEN mode Interrupt (jump to address 8 at page0) No function Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) NORMAL mode Interrupt (jump to address 8 at page0) No function Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0)
COUNTER1 time out IOCF bit1=1 And "ENI" PORT70 Only at IRC mode or crystal mode (at P70S = 0) PORT71 Only at P71S = 0 PORT73 IOCF bit3 bit7 =1 And "ENI" ADI IOCE bit5 = 1 And "ENI PWM1 IOCE bit4 = 1 And "ENI
RESET and Jump to address 0
RESET and Jump to address 0 RESET and Jump to address 0
No function
No function Interrupt (jump to address 8 at page0)
No function
PORT70 's interrupt function is controlled by IOCF bit 3. It's falling edge or rising edge trigger (controlled by CONT register bit7). PORT71 's interrupt function is controlled by IOCF bit 4. It's falling edge trigger. PORT73 's interrupt function is controlled by IOCF bit 7. They are falling edge trigger. ADI interrupt source function is controlled by RE PAGE0 bit 5. It is rising edge trigger after ADC sample complete.
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* This specification is subject to change without notice.
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VII.4 I/O Port
The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O data registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.9.
PCRD
Q
P R C L
D CLK PCWR
Q
PORT
Q
P R C L
D CLK PDWR
IOD
Q
PDRD 0 1 M U X
Fig.9_1 The circuit of I/O port and I/O control register
VDD
VDD
VDD
pull high
PIN
120 ohm
Fig.9_2 The input/output circuit of EM785840 input/output ports
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* This specification is subject to change without notice.
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VII.5 RESET
The RESET can be caused by (1) Power on reset (2) WDT timeout. (if enabled and in GREEN or NORMAL mode) (3) /RESET pin pull low (At P71S = 1). Once the RESET occurs, the following functions are performed. * The oscillator is running, or will be started. * The Program Counter (R2) is set to all "0". * When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared. * The Watchdog timer and prescaler counter are cleared. * The Watchdog timer is disabled.
VII.6 Wake-up
The controller provided sleep mode for power saving : SLEEP mode, RA(7) = 0 + "SLEP" instruction The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or PLL control (which has enable register), user has to turn it off by software. Wake-up from SLEEP mode (1) WDT time out (2) External interrupt (3) /RESET pull low All these cases will reset controller , and run the program at address zero. The status just like the power on reset.
VII.7 Interrupt
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.
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* This specification is subject to change without notice.
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EM78P5840/5841/5842 8-bit Micro-controller
VII.8 Instruction Set
Instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. INSTRUCTION BINARY 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0000 0001 0010 0011 0100 rrrr 0000 0001 0010 0011 HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R OPERATION No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONT A IOCR A R2+A R2 bits 9,10 do not clear AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R STATUS AFFECTED None C None T,P T,P None None None None None None None Z,C,DC None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Instruction cycle 1 1 1 1 1 1 1 1 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 01rr rrrr 1000 0000 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr
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* This specification is subject to change without notice.
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0 0 0 0 0 0101 0101 0101 0101 0110 00rr 01rr 10rr 11rr 00rr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1E8k 1Fkk INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1) R(0) C, C A(7) R(n) R(n-1) R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0) R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP] (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP] 001H PC K->R5(4:0) k+A A Z Z None None C C C C None None None None None None None None None None None Z Z Z None Z,C,DC None None Z,C,DC 1 1 2 if skip 2 if skip 1 1 1 1 1 1 2 if skip 2 if skip 1 1 2 if skip 2 if skip 2 2 1 1 1 1 2 1 1 1 1
0 0110 01rr 0 0110 10rr 0 0110 11rr 0 0111 00rr 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0111 0111 0111 100b 101b 110b 111b 00kk 01kk 1000 1001 1010 1011 1100 1101 1110
01rr rrrr 10rr rrrr 11rr rrrr bbrr rrrr bbrr rrrr bbrr rrrr bbrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0001
1 1110 100k kkkk 1 1111 kkkk kkkk
** 1 Instruction cycle = 2 main CLK
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* This specification is subject to change without notice.
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VII.9_1 Code Option
EM78P5840 CODE Option Register
12 11 10 9 8 7 6 5 4 IR3 IR2 IR1 IR0 P71S P70S OSCM1 OSCM0 IRC2S 3 MER 2 1 1 1 0 /POT0
Bit 0 (/POT0): program ROM protect option. If set 1 to the bit, program memory can be access; else if clear this bit , program memory can not be access. Bit 3(MER) : Memory error recover function 0 disable memory error recover function 1 enable memory error recovery function If user enable memory error recovery function, MCU will improve effect from environment noise. Bit 4 (IRC2S): Internal RC oscillating frequency (for system CLK) select. 0 2M Hz 1 4M Hz Bit5~Bit6 (OSCM0~OSCM1): EM78P5840 oscillating mode select. OSCM1 0 0 1 OSCM0 0 1 X Oscillating mode IRC mode ERIC mode Crystal mode
Bit 7 (P70S): PORT70 function select bit: OSCM1 OSCM0 P70S 0 0 X 0 1 X 1 X 1 1 X 0
PORT70 status General Purpose IO OSC input, please cascade resister to AVDD PLLC output, please cascade capacitor to AVSS General Purpose IO, PLL function will disable
Bit 8 (P71S): PORT71 function select bit: 0 /RESET pin selected.. 1 General purpose INPUT port "PORT71" selected Bit 9~ Bit12 (IR0~IR3): By setting IR0~IR3, IRC mode's oscillating frequency can be adjust. Next table show the trimming code table of IRC frequency. IR3~IR0 Frequency 0000 1.05*F 0001 1.10*F 0010 1.15*F 0011 1.20*F 0100 1.25*F 0101 1.30*F 0110 1.35*F 0111 1.40*F 1000 0.65*F 1001 0.70*F 1010 0.75*F 1011 0.80*F 1100 0.85*F 1101 0.90*F 1110 0.95*F 1111 1.0*F * "F" means the frequency of IRC output.
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* This specification is subject to change without notice.
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VII.10 PWM (Pulse Width Modulation)
(1) Overview In PWM mode, both PWM1 and PWM2 pins produce up to a 10-bit resolution PWM output (see. Fig.10 for the functional block diagram). A PWM output has a period and a duty cycle, and it keeps the output in high. The baud rate of the PWM is the inverse of the period. Fig.11 depicts the relationships between a period and a duty cycle.
DL2H + DL2L
latch To PWM1IF
Fosc 1:2 1:8 1:32 1:64
DT2H + DT2L Comparator MUX
TMR1H + TMR1L
reset
Duty Cycle Match
PWM1 R S
IOC6
Q
Comparator
T1P0 T1P1 T1EN
Period Match
PRD1 Data Bus
DL2H + DL2L
latch
Data Bus
To PWM2IF
T2P0 T2P1 T2EN
DT2H + DT2L
Comparator
Duty Cycle Match
PWM2 Fosc 1:2 1:8 1:32 1:64
TMR2H + TMR2L
reset
R S
Q
MUX Comparator
IOC6 Period Match
PRD2
Fig.10 The Functional Block Diagram of the Dual PWMs
Period
Duty Cycle DT1 = TMR1
PRD1 = TMR1
Fig.11 The Output Timing of the PWM (2) Increment Timer Counter (TMRX: TMR1H/TWR1L or TMR2H/TWR2L) TMRX are ten-bit clock counters with programmable prescalers. They are designed for the PWM module as baud rate clock generators. TMRX can be read, written, and cleared at any reset conditions. If employed, they can be turned down for power saving by setting T1EN bit to 0. (3) PWM Period (PRDX : PRD1 or PRD2) The PWM period is defined by writing to the PRDX register. When TMRX is equal to PRDX, the following events occur on the next increment cycle: * TMRX is cleared. * The PWMX pin is set to 1.
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* This specification is subject to change without notice.
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* The PWM duty cycle is latched from DT1/DT2 to DTL1/DTL2. < Note > The PWM output will not be set, if the duty cycle is 0; * The PWMXIF pin is set to 1. The following formula describes how to calculate the PWM period: PERIOD = (PRDX + 1) * 4 * (1/Fosc) * (TMRX prescale value ) Where Fosc is system clock (4) PWM Duty Cycle ( DTX: DT1H/ DT1L; DTL: DL1H/DL1L) The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded at any time. However, it cannot be latched into DTL until the current value of DLX is equal to TMRX. The following formula describes how to calculate the PWM duty cycle: Duty Cycle = (DTX) * (1/Fosc) * (TMRX prescale value) (5) PWM Programming Procedures/Steps Load PRDX with the PWM period. (1) Load DTX with the PWM Duty Cycle. (2) Enable interrupt function by writing IOCF PAFE0, if required. (3) Set PWMX pin to be output by writing a desired value to IOCC PAGE0. Load a desired value to R5 PAGE3 with TMRX prescaler value and enable both PWMX and TMRX. (6) Timer Timer1 (TMR1) and Timer2 (TMR2) (TMRX) are 10-bit clock counters with programmable prescalers, respectively. This is designed for the PWM module as baud rate clock generators. TMRX can be read, written, and cleared at any reset conditions. The figure in the next page shows TMRX block diagram. Each signal and block are described as follows:
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Fosc 1:2 1:8 1:32 1:64
To PWM1IF
MUX TMR1X
reset Period Match
Comparator
T1P0 T1P1 T1EN
PRD1 Data Bus Data Bus
PRD2
T2P0 T2P1 T2EN
Comparator
Period Match
Fosc 1:2 1:8 1:32 1:64
TMR2X MUX
reset
To PWM2IF
*TMR1X = TMR1H + TMR1L; *TMR2X = TMR2H +TMR2L
Fig.12 TMRX Block Diagram * Fosc: Input clock. * Prescaler (T1P0 and T1P1): Options of 1:2, 1:8, 1:32, and 1:64 are defined by TMRX. It is cleared when any type of reset occurs. * TMR1X (TMR1H/TWR1L):Timer X register; TMRX is increased until it matches with PRDX, and then is reset to 0. TMRX cannot be read. * PRDX (PRD1): PWM period register. When defining TMRX, refer to the related registers of its operation as shown in prescale register. It must be noted that the PWMX bits must be disabled if their related TMRXs are employed. That is, bit 6 of the PWMCON register must be set to `0'. Related Control Registers(R5 PAGE3) of TMR1 and TMR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 PWM2E PWM1E T2EN T1EN T2P1 T2P0 T1P1 Bit 0 T1P0
Timer programming procedures/steps Load PRDX with the TIMER period. Enable interrupt function by writing IOCF PAGE0, if required Load a desired value to PWMCON with the TMRX prescaler value and enable both TMRX and disable PWMX.
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* This specification is subject to change without notice.
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VII.11 Oscillator
The EM78P5840 can be operated in two different oscillator modes, each of them are crystal mode and RC mode. Users can select one of them by setting code option. The descript of these two oscillator mode are as below: (1) Crystal mode: For crystal mode operation, one crystal and tow capacitances is needed for external circuit. In this mode, eFTP5840 can be run in three active mode include normal mode, green mode and sleep mode. The advantages of this mode are low power consumption (in green mode) and with more precise main CLK. Next figure show the application circuit of crystal mode. Pin XIN and pin XOUT can be connected with a crystal directly to generate oscillation. By clear code option"P70S" to 0, PORT70 can switch to general IO (disable PLL function and EM78P5840 can not active on normal mode); /RESET pin can switch to PORT71 if clear "P71S" to 0.
NIX 5840 H PF e T UOX
Fig 13: Application circuit of Crystal mode
(CPU stop) Sleep Mode
IRC1 : ON 32K : un-active PLL : turn off
Reset
RA page0 bit7 = 0 & run"SLEP"
Reset RESET operation
Green Mode
IRC1 : ON 32K : oscillating PLL : turn off
PLLEN bit = 1
Normal Mode
IRC1 : ON 32K : oscillating PLL : turn on
Reset release Reset
PLLEN bit = 0
Fig 14: The relative of Crystal mode's normal, green and sleep mode
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* This specification is subject to change without notice.
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(2) IRC mode: For some applications that do not require precise timing calculation, the RC oscillator could offer users with an effective cost savings. eFTP5840 offer a versatile internal RC mode with default frequency value of 4M and 2MHz. In this mode, PLLC, XIN, XOUT and /RESET pins can defined to general purpose IO. The IRC frequency will drift with the variation of voltage, temperature and process: The frequency deviation of IRC mode: Freq range (before adjust IR0~IR3) Internal RC Freq range (after adjust IR0~IR3) (IR0~IR3 = 1111) 4M Hz 2.8M ~ 5.2M 3.6M ~ 4.4M 2M Hz 1.4M ~ 2.6M 1.8 M ~ 2.2M *The frequency of IRC output can be adjust by setting IR0~IR3 in code option. By setting IR0~IR3, the frequency deviation can be compensation. Please refer to code option to detail. In IRC mode, PORT60, PORT61 and PORT70 are defined to bi-direction IO. By clearing P71S in code option to 0, /RESET pin can also switch to INPUT pin (PORT71). In IRC mode, only two active modes can be achieved, please refer to next figure to detail. (3) ERIC mode: ERIC mode is equipped with an internal capacitor and an external resistor (connected to VDD). The internal capacitor functions as temperature compensator. In order to obtain more accurate frequency, a precise resistor is recommended. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. Besides, the package types, and the way the PCB is layout, have certain effect on the system frequency. About the application is as below: The frequency deviation of ERIC mode: Internal C, external R Freq range 4M Hz (R=51K) 3.5M ~ 4.4M 2M Hz(R=100K) 1.8M ~ 2.2M
VDD R
ERIC
EM78P5840
Fig 15: Application circuit of ERIC mode ERIC's oscillating frequency will base on IRC2's CLK (determined on code option "IRC2S"). For example, if IRC2S = 0, IRC2's oscillating frequency is 2M Hz. At this time, by adjusting R, system CLK will be changed. But the system CLK will always greater than 2M. That is to say, system CLK can only be adjusted between 2M to 6M. Next two table show the corresponding between system oscillating CLK and the value of external resister. The corresponding between system oscillating CLK and the value of external resister Frequency (Hz) External resister (ohm) Operating Voltage (VDD) 6M 34K 3.0 ~5.5 V 5M 41K 2.8 ~5.5 V 4M 51K 2.5 ~5.5 V 3.58M 57K 2.2 ~5.5 V 2.1M 97K 2.2 ~5.5 V *Only 2 types active mode (normal mode and sleep mode) are permitting in RC mode.
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* This specification is subject to change without notice.
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(CPU stop) leep S Mode Reset
ERC or IRC2 : ON IRC1 : ON PLL : turn off
RESET operation
run"LEP" S
Reset Normal Mode
ERC or IRC2 : ON IRC1 : ON PLL : turn off
Fig 15: The relative of IRC and ERIC mode's normal and sleep mode
VII.12 Power on Considerations
Any micro-controller is not guaranteed to start to operate properly before the power supply stabilizes at its steady states. EM78P5840 power on reset voltage range is 1.6V ~ 2.0V. Under customer application, VDD must drop to below 1.6V and remains OFF for 10uS before power can be switched on again. This way, EM78P5840 will reset and work normally. The extra external reset circuit will work well if VDD can rise at very fast speed (50mS or less). However, under most cases where critical applications are involved, extra devices are required to assist in solving the power-up problems.
VII.13 External Power on Reset circuit
By Setting code option "P71S" to 1, /RESET pin is selected. Next figure is an external RC to produce the reset pulse. The pulse width should be kept long enough for VDD to reach minimum operation voltage. The diode D acts as a short circuit at the moment of power down. The capacitor C will discharged rapidly and fully.
VDD R /RESET C D
Fig 15: External power on reset circuit 1
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* This specification is subject to change without notice.
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POR reset voltage is influenced in process or temperature. For some application, a constant reset voltage is important. Next circuit will support a adjust reset voltage. By adjusting R41 and R46, POR reset voltage will be a constant (Vpor) and the potential on /RESET pin will drop to 0 when VDD drop to below Vpor. Next plot show the relative between VDD and Vpor. When R41 = 3.9M ohm and R46 = 910K ohm, /RESET will keep to 0 if VDD is below 2.24V and will active after VDD upper to 2.1V.
VDD
R41 3M9 R44
R42 2M2
R43 330K RESET
22M Q3
Q2 C31 C1815 104 S10 RESET
R46 910K
C1815
Fig 16: External power on reset circuit 2
VDD
2.24V 2.1V VDD /RESET
T
Fig 17: The relative between VDD and Vpor
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* This specification is subject to change without notice.
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VIII. Absolute Operation Maximum Ratings
RATING DC SUPPLY VOLTAGE INPUT VOLTAGE OPERATING TEMPERATURE RANGE SYMBOL VDD Vin Ta VALUE -0.3 To 6 -0.5 to VDD +0.5 0 to 70 UNIT V V J
IX. DC Electrical Characteristic
(Ta = 25C, AVDD=VDD=5V5%, VSS=0V) Parameter Symbol Condition Min Input leakage current for input IIL1 VIN = VDD, VSS pins Input leakage current for biIIL2 VIN = VDD, VSS directional pins Input high voltage (except P71) VIH 2.5 Input low voltage (except P71) VIL P71 Input high voltage VIH 2.0 P71 Input low voltage VIL Input high threshold voltage VIHT /RESET, TCC 2.0 Input low threshold voltage VILT /RESET, TCC Clock input high voltage VIHX OSCI 3.5 Clock input low voltage VILX OSCI Output high voltage for VOH1 IOH = -6mA 2.4 PORTC1~PORTC2 Output high voltage for VOH2 IOH = -10mA 2.4 PORT60~PORT67; PORT7 Output high voltage for VOH3 IOH = -15mA 2.4 PORT9 Output low voltage for VOL1 IOH = 6mA PORTC1~PORTC2 Output low voltage for VOL2 IOH = 10mA PORT60~PORT67; PORT7 Output low voltage for VOL3 IOH = 15mA PORT9 Pull-high current IPH Pull-high active input pin at VSS Power down current ISB1 All input and I/O pin at VDD, (SLEEP mode) output pin floating, WDT disabled Low clock current ISB2 CLK=32.768KHz, All analog (GREEN mode) circuits disabled, All input and I/O pin at VDD, output pin floating, WDT disabled Operating supply current ICC1 /RESET=High, (Normal mode) CLK=3.582MHz, All analog circuits disabled, output pin floating Typ Max 1 1 Unit A A V V V V V V V V V V V 0.4 0.4 0.4 -10 1 -15 4 V V V A A A
0.8 0.8 0.8 1.5
25
35
1.5
2.5
mA
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* This specification is subject to change without notice.
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XI. AC Electrical Characteristic
CPU instruction timing (Ta = 25C, AVDD=VDD=5V, VSS=0V) Parameter Input CLK duty cycle Instruction cycle time Device delay hold time TCC input period Watchdog timer period Symbol Dclk Tins Tdrh Ttcc Twdt Condition 32.768kHz 3.582MHz Note 1 Ta = 25C (Tins+20)/N 16-30% Min 45 Typ 50 60 550 16 16 Max 55 Unit % us ns ms ns ms
16+30%
Note 1: N= selected prescaler ratio. ADC characteristic (VDD = 5V, Ta = +25C, for internal reference voltage) Parameter Symbol Condition Upper bound offset voltage Vofh Lower bound offset voltage Vofl *These parameters are characterized but not tested. * About ADC characteristic, please refer to next page. Timing characteristic (AVDD=VDD=5V,Ta=+25C) Description Oscillator timing characteristic Crystal start up 32.768kHz 3.579MHz PLL Symbol Tosc Min 400 5 Trst Tdrs 3 18 Typ Max 1500 10 Unit ms us uS mS Min Typ 44 32 Max 52.8 38.4 Unit mV mV
Timing characteristic of reset The minimum width of reset low pulse The delay between reset and program start
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* This specification is subject to change without notice.
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VDD
OSC
Toscs
Power on reset
Trst
/RESET
Tdrs Tdrs
Program Active
The relative between OSC stable time and power on reset
EM78P5840 operation voltage(X axis
min VDD ; Y axis
main CLK):
MHz 14.3 3.58
2.2
3.6
5.5
V
Fig.18 The relative between operating voltage and main CLK
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* This specification is subject to change without notice.
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EM78P5840/5841/5842 8-bit Micro-controller EM785840's 10 bit ADC characteristic
EM785840 build in 10 bit resolution, multi channel ADC function. In ideal, if ADC's reference voltage is 5V, the ADC's LSB will be 5V/1024. But in practical, for some physics or circuit's character, some un-ideal will effect the converter result. As the next figure, offset voltage will reduce AD's converter range. If AD's input voltage less than VOFL, ADC will output 0; in opposition, if input voltage is larger than (VDD-VOFH), ADC will output 1023. That is to say the physics AD converter range will replace by (VDD-VOFH+LSB-VOFL+LSB). If we defined that VRB = VOFL - LSB and VRT = VDDVOFH+LSB, the physics LSB is: LSB = (VRT - VRB) / 1024 = (VDD - (VOFH+VOFL) ) / 1022 For real operating, please think about the effect of AD's offset voltage. If converter the range of (VRT - VRB), the AD converter's opposite result will be precised.
10-bit ADC
VDD VRT Min. input for ADC output = 1023 VOFH
(For 10-bit ADC, internally it takes this range to average 1024 steps)
Min. input for ADC output = 1 VOFL VRB 0V
Fig.19 The relative between ADC and offset voltage
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* This specification is subject to change without notice.
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XII. Timing Diagrams
ins
Fig.20 AC timing
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* This specification is subject to change without notice.
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XIII. EM78P5840 OTP ROM burning pins
One time programmable ROM burner pin OTP PIN NAME MASK ROM PIN NAME VDD AVDD VPP /RESET DINCK P65 ACLK P64 PGMB P63 OEB P62 DATA P73 GND AVSS P.S.
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* This specification is subject to change without notice.
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Appendix: Package spec of EM78P5840/5841/5842
EM78P5840M
EM78P5840P
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* This specification is subject to change without notice.
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EM78P5841M
EM78P5841P
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* This specification is subject to change without notice.
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EM78P5842M
EM78P5842P
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* This specification is subject to change without notice.
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